A pipelined analog-to-digital (AD) conversion circuit includes unit conversion circuits in a plurality of stages and an encoder which encodes output digital codes from the unit conversion circuit at each stage to generate an output digital code. The unit conversion circuit includes a sub ADC which performs AD conversion of an analog input signal, and a switched capacitor circuit which amplifies the analog input signal and changes it in accordance with the AD conversion result. The pipelined AD conversion circuit controls unit conversion circuits in a plurality of stages to be in sample periods and hold periods sequentially from the first stage in a pipelined manner, thereby generating output digital codes with high accuracy.
The pipelined AD conversion circuit is described in, for example, Mehdi Saberi, and Reza Lotfi “A Capacitor Mismatch- and Nonlinearity-Insensitive 1.5-bit Residue Stage for Pipelined ADCs” pages 677-680, 2007 IEEE.
Japanese Laid-open Patent Publication No. 2008-141396 discloses a cyclic AD conversion circuit which uses a single comparator in a time-divisional manner.
A conventional switched capacitor circuit has two kinds of capacitors which are designed so that their capacitances are the same. The capacitances of the capacitors include relative errors caused by manufacturing variations. The relative errors cause an error in a voltage of an output signal, leading to a reduction in conversion accuracy. Increasing the size of a capacitor to increase the capacitance enables the relative error in the capacitance of capacitors to be reduced. A large capacitance of a capacitor, however, gives rise to increases in the sample period and hold period of a switched capacitor circuit. As a result, in a pipelined AD conversion circuit, the conversion speed decreases, the power consumption increases, and the exclusive area used on a chip increases. In other words, there is a trade-off relationship between the relative error and the conversion speed, power consumption and the exclusively occupied area in regard to the capacitance of a capacitor.